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Silicon Whiteboard Corporate Backgrounder
Silicon Whiteboard is a training and consulting company located in San Diego, California, USA. We provide training courses in ASIC, FPGA, Hardware and Software Design, Debug and Production Testing using deep submicron foundry technologies such as 90, 65 and 45nm geometries. Courses including Hardware and Software languages such as VHDL, Verilog, System Verilog, System C, C, C++, Perl, TCL/Tk, etc. are offered to our Corporate customers. ASIC/FPGA/Hardware/Software Design Services are offered on a contract basis. We are currently providing on-site ASIC and FPGA design consulting services to our corporate customers. With wireless and wired communications background, we are experts in Low power and high performance ASIC/FPGA design and implementation from concept to GDSII tapeout. We are also experienced in mixed-signal modeling and implementation. We work with the Cadence Low Power Logic and Physical design tools using the CPF methodology, Synopsys VMM (with System Verilog) for Systems Verification and all other major EDA design tools. If desired, customers can choose either to provide design tools and facilities for our consulting services, or to farm out an entire project for us to complete with our own tool sets. We have good relationship with major and minor deep submicron foundries all over the world and can negotiate shuttle and other mask making and fabrication arrangments. We also have a partnership with another San Diego based Physical Design Service Provider for larger scaled design projects. Some basic corporate training materials were jointly developed by Silicon Whiteboard and Blue Pacific Computing, Inc. (www.bluepc.com), a San Diego, CA company. To further lower the cost of design services and to leverage test and manufacturing facilities in Asia, an overseas design center is under consideration.
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Consultant Bios
Kameron Wong, CEO & Founder, Principal Consultant and Trainer
Proven leader of several startup companies and an entrepreneur, with over 20 years of experience. Directed product development and hands-on expertise from concept to design to GDSII tapeout using cutting edge semiconductor technologies such as 65nm CMOS processes, with focus on LOW POWER and HIGH PERFORMANCE digital design and development. Winner of "Innovator of the year, 2004 – Unlicensed Wireless Communications Design". Well versed in different development/production phases including silicon design and layout, board level prototyping with FPGA (from Spartan to Xilinx latest Virtex-5 and Altera Stratix devices), lab testing/debug and production testing and characterization, foundry relationship with TSMC, UMC, Fujitsu and others. Product spectrum ranges from single-chip UWB CMOS devices to 802.11, Bluetooth handheld devices, mobile phones, CMOS pixel sensor controller, and other wireless communication devices. Experienced corporate trainer in all aspects of digital ASIC, FPGA design with VHDL, Verilog, System Verilog, System C, and other Advanced Digital and Hardware Design Techniques. Currently Founder and CEO of Silicon Whiteboard, a consulting and corporate training company. Formerly Director of Digital Design Engineering, Co-founder, Principal Engineer at several startup companies. Holds MSEE and BSEE degrees.
Principal ASIC and FPGA Design Consultant
Over 20 years of experience in ASIC and FPGA design for wired and wireless communication products. Completed numerous high complexity designs using state of the art development tools. Experienced in all aspects of current digital ASIC, FPGA design flow with VHDL, Verilog, and other advanced digital and hardware design techniques. Expert in digital filter design from defining requirements to final implemented design. Completed several ASIC and FPGA projects related to real-time digital video processing. Developed digital Baseband for several wireless communication standards including Bluetooth, 802.11, UWB, & DVB. Experienced with most current FPGA devices. Familiar with most wireless communication techniques such as OFDM, OQPSK, QPSK, QAM, BPSK, GFSK, and DSSS. Previous Positions Chief Engineer, Director of Hardware Engineering, Director of ASIC and hardware design and ASIC Manager. Holds 5 patents related to hardware design for communication systems. Holds MSEE and BSEE degrees.
Principal Hardware Design Consultant
"IITian" (Graduate from IIT, India). Over 20 years of experience in digital and analog PCB Board Hardware, FPGA and ASIC designs. Conducted Digital and analog hardware projects from concept to production such as medical electronics, power electronics, networking, wireless, consumer, industrial, microprocessors (8-bit to 64-bit to multi-core). Well versed in Assembly (ARM and other processors), C/C++ Firmware including device drivers to protocol stack and application software development. Specialized in embedded system architecture, board design, product design and certification. Successfully implemented FPGA, CPLD and ASIC designs spanning across architecture, RTL coding, validation and debugging phases. Experienced in highly price-sensitive and competitive Indian Industry. Holds MSEE and BSEE degrees.
Principal Design Verification Consultant
Over 12 years of experience in design and verification. Specialized in high performance design and verification with experience in all aspects of front-end ASIC and FPGA design. Well-versed in SystemVerilog/VMM and SystemC verification, along with VHDL and Verilog design. Was a Panelist on the Synopsys VMM User Forum at DAC 2007 in San Diego. Currently working on a white paper which was accepted for SNUG San Jose 2008 entitled "Using DPI and VMM to Leverage Verification Environment to Enable Early Testing, Emulation and Validation." Experienced in many industries and technologies, including network accelleration ASIC's, UWB/wireless USB, low-power mobile SOC's, network processors, CDMA physical layer, wideband radar receivers, and missile guidance systems. Previous positions include Staff and Senior Design and Verification Engineer at various companies. Holds BS Electrical Engineering.
Principal VLSI Physical Design, Interconnect and DFM Consultant
Over the past 19 years, performed the chip-level post-layout processing, physical verification, and GDSII submission of 23 ASIC designs to TSMC, IBM, UMC, Chartered, and Tower. Knowledgeable in tradeoffs and strategies for implementing effective DFY (Design For Yield) design methodologies for 90, 65, and 45nm CMOS technologies at the cell-, block- and chip-level, based on specific DFM (Design For Manufacturing) guidance provided by a foundry. Extensive experience in floorplanning and automating the chip-level assembly of single- and dual-IO Ring ASICs with inline, staggered, or tri-tier wirebond IOs, with peripheral or area array flipchips, and ASICs targetting Chip Scale design rules. Well-versed in the use of single or multiple Re-Distribution Layers for Interconnect to: a) dramatically reduce IR-drop by enhancing chip-level supply distribution, b) reduce the overall cost of a multi-layer ASIC, or c) retro-fit an existing wirebond ASIC for flipchip packaging. Expert in evaluating and preparing hard IP macros with VSIA IP tags for automated Place & Route. Experienced in installing, running, and trouble-shooting Cadence, Synopsys, and Assura runsets for DRC, LVS, and Pattern Density Generation. Knowledgeable in the chip-level integration of seal rings, crack stops, and scribe lanes around chips (or chiplets) to form a reticle designed to maximize raw die count per wafer. Programming languages include Cadence SKILL, Perl, and shell scripting for VLSI CAD and EDA applications. Holds BSEE, MSEE, and PhD degrees in Electrical Engineering.
Principal Mixed-signal, Analog and Modeling Consultant
Over 25 years of experience in Integrated Circuit and System-on-Chip design, test, wireless systems and software. Designed digital and analog blocks on more than 20 IC and SoC projects. Developed analog/RF mixed-signal modeling methodology using standard Verilog and VHDL. Wireless projects included 802.11, 3G/WCDMA, Bluetooth and Military SDR. Led a global team of 100 people in U.S., Europe and Asia who integrated hardware, firmware and software for a Bluetooth wireless module into the Hewlett Packard iPAQ PDA; Managed and staffed digital design, system design and applications groups working on various wireless systems. Was responsible for all aspects of groups including: planning, budgets, design, modeling, reference design boards, manufacturing, test, customer support and outsourcing. Reduced cost of IC test over 90 per cent by developing PC-based test systems. Created EDA tools for Verilog, VHDL and SystemC. Wrote software and set up web-based distribution that provided the tools to over 30,000 students and engineers. Developed and taught Verilog, VHDL, SystemC and C/C++ classes for UCSD, Cadence and Synopsys. Presented over 50 classes at Fortune 500 companies such as Texas Instruments, Hewlett Packard, Infineon, Nokia and Lockheed Martin. Wrote and marketed a book for system/software engineers and managers who want to understand the basics of Electronic System Level (ESL) design with Hardware Description Languages: Hardware Design for Software People in the SoC Era. Previous positions Design Manager, Co-founder of a semiconductor design services and training company, Analog Modeling Consultant, and Test Engineering Manager. Holds Ph.D., MSEE, BSPhy.
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